1. Field of the Invention
The present invention relates to a nonvolatile memory which can write and erase data and, more particularly, to a nonvolatile memory from which data can be read at proper time.
2. Description of the Related Art
In general, in erasable programmable read only memories (EPROMs), data is stored in the form of presence or absence of electric charges at floating gates of nonvolatile transistors serving as memory cells. The erasure of data which has been written is performed by irradiation with ultraviolet rays and data can be written into again.
FIG. 1 illustrates a circuit arrangement for reading out data in a prior art EPROM. In the Figure, reference numeral 12 designates a memory cell formed of a nonvolatile transistor with a floating gate. Memory cell 12 has its gate connected to a word line WL, its source connected to ground potential Vss and its drain connected to a bit line BL via a selecting transistor (not shown). Bit line BL is connected to power supply voltage Vcc via a load 14. Bit line BL is connected to a latch type of sense amplifier circuit 22 comprised of two clocked inverters 16 and 18 and an inverter 20 for providing read data RD.
In FIG. 2 there is illustrated a timing chart of the above prior-art EPROM. It is assumed here that memory cell 12 is programmed with data beforehand.
To read data, word line WL is selected first. If electrons are not injected into the floating gate at the programming time and thus the threshold voltage is low, memory cell 12 is turned on (time t.sub.1) so that bit line BL is discharged through cell 12. Hence, the potential of bit line BL is lowered gradually down to a "LOW" level. On the other hand, if electrons are injected into the floating gate at the programming time and thus the threshold voltage is rendered high, memory cell 12 is not turned on. Thus, bit line BL is charged through load 14 up to a "HIGH" level.
When clock signal CK goes to a "HIGH" level (time t.sub.2), clocked inverter 16 is brought into operation to take in data appearing on bit line BL. Next, when clock signal CK goes to a "LOW" level (time t.sub.3), a positive feedback circuit formed of clocked inverter 18 and inverter 20 operates to latch the data taken in by clocked inverter 16. The data is output as readout data RD.
When a memory cell whose floating gate has been injected with electrons is selected as described above, the memory cell cannot hold the completely off state in practice. For this reason, a little current flows between the drain and source so that bit line BL is discharged gradually. Thus, the potential of bit line BL is lowered as shown in FIG. 3. After the lapse of a constant time t (time t.sub.13) from when the potential of word line WL goes to "HIGH" level (time t.sub.11), ,the potential of bit line BL will become lower than 1/2Vcc, and 1/2Vcc is the threshold voltage of clocked inverter 16.
It is assumed that clock signal CK remains at the "HIGH" level (at time t.sub.12) even after the lapse of constant time t (at time t.sub.13) from the time when clock CK was raised to "HIGH" level. Then, the output of clocked inverter 16, which should be at a "LOW" level, will be inverted to "HIGH" level. Hence, sense amplifier 22 will latch erroneous data.
In order to prevent sense amplifier 22 from latching erroneous data, the clock signal CK needs to be lowered to "LOW" level before the potential of bit line BL goes lower than 1/2Vcc. However, the time at which the potential of bit line BL goes lower than 1/2Vcc will vary with power supply voltage Vcc and the characteristics of individual memory cells. Moreover, the time need for the potential to drop will be affected by variations in the threshold voltage of a memory cell over time. With a conventional EPROM, therefore, even if it operates properly right after manufacture, the possibility of malfunction will increase with time.
With conventional nonvolatile memory devices, as described above, the time at which the latch type of sense amplifier latches data appearing on a bit line is determined at the circuit design stage. The difficulty with conventional nonvolatile memories is that, even if they operate properly at first, the possibility of malfunction increases with time.